1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to semiconductor devices having a metal electrode.
2. Related Art
Parasitic gate capacitance between a gate electrode and a contact undesirably decreases the speed of the device. The parasitic gate capacitance can be reduced by reducing the thickness of the gate electrode. A common gate electrode includes polysilicon and a silicide formed over the polysilicon. If the polysilicon is reduced in thickness too much the polysilicon will be consumed during the silicidation process. This undesirably results in the gate electrode being silicide only. Thus, the silicide will be in contact with the underlying gate dielectric resulting in an undesirable threshold voltage. Therefore, a need exists for a process that decreases parasitic gate capacitance between a gate electrode and a contact without a silicide being in contact with the underlying gate dielectric.